Recently, in electronic devices with a semiconductor device incorporated therein, not only there has been a tendency to high speed, high function, and high packaging density, but also efforts have been made for the reduction of thickness and weight. Particularly, flip chip packaging of a semiconductor chip (semiconductor element) with LSI, etc. incorporated therein is effective for the attainment of high speed and thickness reduction.
Flip chip packaging methods are broadly classified into the following two methods. (1) Gold stud bumps are formed on peripheral electrodes (e.g., aluminum electrodes) of a semiconductor chip by the wire bonding method and thereafter the gold stud bumps (gold salient electrodes) are bonded to a mounting substrate through a thermosetting resin such as ACF (Anisotropic Conductive Film) or NCF (Non Conductive Film), or the gold stud bumps and wiring lines (leads) on a mounting substrate are connected together using solder, followed by sealing with an insulating resin. (2) There is adopted a WPP (Wafer Process Package) method wherein film forming and patterning steps are repeated for a wafer in the manufacture of a semiconductor chip to form a re-wiring layer which provides connection between peripheral electrodes on the semiconductor chip and lands for solder electrodes arranged in a lattice shape, and solder bump electrodes are formed on the lands for solder electrodes. After subsequent division into individual chips, each of the chips is connected to a substrate through the solder bump electrodes.
The above flip chip packaging methods give rise to the following problems. For preventing signal delay caused by an increase of the wiring length, peripheral electrodes on a semiconductor chip are arranged along an area where input/output circuit elements of the semiconductor chip are formed, so are generally arranged at a small spacing (pitch) in a narrow area on a main surface of the semiconductor chip. Therefore, in the above method (1) wherein bump electrodes are formed directly on the peripheral electrodes of the semiconductor chip, the pitch of the bump electrodes thus formed is small and it is accordingly required to use a build-up type packaging substrate which is more expensive than the ordinary type of packaging substrates.
In the above method (2), by forming a re-wiring layer, it becomes possible to arrange lands for solder electrodes in a lattice shape of plural rows and columns over a wide main surface of a semiconductor chip, so that the spacing between adjacent solder bump electrodes also becomes wider. However, since the manufacturing process is applied, including defective ships in a state of wafer, an increase of cost results, and it is difficult to form a mechanism for relaxing a thermal stress which is induced between the packaging substrate and the semiconductor chip in the foregoing WPP method.
As the packaging substrate for the semiconductor device there generally is employed a ceramic substrate or a printed substrate. In these packaging substrates, the pitch of electrodes for connection with the semiconductor device is about 130 to 160 μm, thus making it impossible to connect them with peripheral electrodes on the semiconductor chip side having a pitch of 80 to 100 μm directly by flip chip bonding.
For the printed substrate, therefore, there usually is adopted a build-up method capable of forming fine electrodes, as a substitute for the conventional laminate method.
However, the build-up method is more complicated in the manufacturing process than the laminate method and the resulting substrate is 1.7 to 2 times more expensive than the substrate obtained by the laminate method.
Therefore, the present inventor has studied changing electrodes on the semiconductor chip side from peripheral electrodes to area array bump electrodes arranged in a lattice shape of plural rows and columns on a main surface of a semiconductor wafer to widen the electrode pitch and thereby permit the use of a printed substrate fabricated by the less expensive laminate method. On the basis of this study the present inventor accomplished the present invention.
In Japanese Unexamined Patent Publication No. 2000-58594 there is disclosed a semiconductor device having a structure wherein a semiconductor chip is mounted through an adhesive onto a tape as a bump substrate having plural solder balls for substrate packaging and wherein grooves are formed in the tape surface where the solder balls are formed, allowing stress to be dispersed by the grooves.
It is an object of the present invention to provide a semiconductor device having area array bump electrodes suitable for flip chip packaging and a method of manufacturing the same.
It is another object of the present invention to provide inexpensively a semiconductor device having area array bump electrodes suitable for flip chip packaging.
It is a further object of the present invention to provide a semiconductor device having a stress relaxing structure between bump electrodes arranged in a lattice shape and a semiconductor chip, and a method of manufacturing the same.
The above and other objects and novel features of the present invention will become apparent from the following description and the accompanying drawings.